1. Field of the Invention
This invention relates to the making of electronic components such as integrated circuit semiconductor devices having electrical interconnection structures within the component and, more particularly, to a self-aligned protective buffer layer over copper damascene interconnects.
2. Description of Related Art
In semiconductor fabrication processes, layers of insulating, conducting and semiconducting materials are commonly deposited and patterned to form integrated circuits (IC). Contact vias, i.e., openings, are also commonly formed in insulating materials known as interlevel dielectrics (ILDs). These vias are filled with conductive material to interconnect electrical devices and wiring at various levels.
Damascene and dual damascene processing similarly involve etching openings to define wiring patterns and contacts in multiple layers of insulating dielectric layers for electrically connecting metallization in one layer to metallization in another layer. In single damascene processing, construction of each interconnect level involves separate patterning and filling of vias (or contacts) and trenches. Dual damascene processing involves patterning both the vias (or contacts) and trenches for each level prior to filling such damascene regions with metallization. These damascene wiring and contact patterns are then filled with a metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. This process is often followed by planarization to remove excess metal material, such as by chemical mechanical polishing.
Recent semiconductor device manufacturing techniques use copper (Cu) as a wiring material, particularly in devices having small feature sizes, due to copper's law resistivity and high resistance to electro-migration. However, copper is often difficult to pattern and use for metal wiring as it is easily oxidized when exposed to air. Oxidation of copper interconnects undesirably increases the resistance of the wiring pattern. Damascene wiring is frequently used for copper interconnection technology whereby trenches and via openings are formed in the insulating dielectric layer and then filled with copper. Chemical mechanical polishing (CMP), or an etch-back process, then planarizes this conductive copper fill to expose the dielectric layer. As a result, the damascene metal wiring pattern remains in the damascene regions and the insulating dielectric layers provide electrical insulation and electrical isolation between the copper wiring elements. However, the damascene copper wiring patterns may still be exposed to air, and thus, be subjected to oxidation. With time and temperature, these oxides ultimately corrode the copper to result in formation of voids in the copper conductor, which are detrimental to the integrated circuit (IC) device and must be avoided.
To avoid both oxidation of the copper and metal diffusion between the copper wiring elements and the insulating dielectric layers, barrier layers are often included in the structure. Barrier layers contain the copper or other metal and provide improved adhesion of the copper lines and vias to the dielectric or other metallization. Cu damascene interconnects require the barrier layers to be deposited in two separate steps. The first deposition is done prior to Cu fill of the patterned damascene trenches and/or vias and is typically a refractory metal such as Ta or TaN that is formed in the via and trench on the sidewalls, trench floor, and at the base of the via. It presents a barrier to the diffusion of metal between the copper filled via and trench and the dielectric, as well as a barrier between such copper metal and the metallization of the underlying or overlying conductor wiring levels. The second barrier deposition is done after Cu CMP (or etchback) and typically coats the exposed Cu surface with dielectric material (such as SiNx and SiCx).
However, it has been found that in copper damascene interconnection structures, the most likely point of failure during line current stress (electromigration) is this copper to dielectric barrier interface. Whereas the electromigration resistance of copper is high enough to sustain the wear-out in normally designed conductor lines, defect-induced electromigration failures have been observed at the interface between the copper and dielectric barrier layer. For instance, wherein copper oxides or hydroxides have been undesirably formed at such interfaces, voids will be formed in the copper layer, which hamper the electromigration characteristics of such copper interconnection. Understandably, current density in these regions is considerably high during actual use, thereby causing early field fails due to defect sensitive electromigration failure.
Further, in damascene processing, prior to barrier deposition and/or depositing metal layers within via and/or via/trench interconnections, a pre-clean step is essential. However, in so doing, underlying copper layers exposed at a bottom of the damascene via and/or via/trench are exposed to air, which forms copper oxides on such surfaces.
Thus, despite repeated efforts, and various schemes in the prior art, manufacturing problems due to defect sensitive electromigration failure and corrosion remain. Better methods for making copper integrated circuit patterns with improved reliability and reduced defect sensitivity need to be developed.